When image data is to be transferred from a host processor (hereinafter, referred to simply as a “host”) to a display panel such as an LCD, generally, the image data is outputted to the display panel after temporarily stored in a frame memory (hereinafter, referred to simply as a “memory”) of an LCDC (LCD Controller). This makes it unnecessary to transfer the image data from the host in a case where there is no update of display data.
However, in seamless processing such as video reproduction, input (writing) of the image data from the host to the LCDC (a frame buffer) is substantially concurrently carried out with output (reading) of the image data from the LCDC to the display panel.
Then, when a difference between transfer rates of the image data cannot be compensated, incomplete image data that is being stored in the memory is outputted to the display panel. This is an overtaking phenomenon, which is called tearing. Further, this output of the incomplete image data to the display panel in a case where tearing occurs causes flickers in image display.
As a conventional technique for suppressing such tearing, Patent Literature 1 discloses a frame rate conversion device. This frame rate conversion device includes memory control means for inputting/outputting data to/from a common memory, overtaking prediction means for predicting a frame where overtaking of data input to/output from the memory occurs, and memory writing control means for stopping writing to the memory in a case where the occurrence of overtaking is predicted by the overtaking prediction means.
Meanwhile, Patent Literature 2 discloses a method for updating a buffer. This method is intended to convey timing information through a communication link between a first processor and a second processor. In this method, the communication link is in a pause mode and a time event is scheduled at the first processor for conveying the timing information to the second processor. Moreover, this method includes the steps of initiating a link wake-up by the first processor at the time when the time event occurs, detecting the link wake-up by the second processor, and synchronizing the first processor and the second processor in terms of the conveyed timing information by using the link wake-up timing that has been detected by the second processor.
Further, Patent Literature 3 discloses a method for avoiding a disturbance in an image due to overtaking of writing/reading in a FI-FO (First in-First out) video memory. In this method, the overtaking phenomenon is avoided by a single device, in an arrangement in which control signals for writing and reading are shifted from each other by at least a storage unit and thereby operation addresses for the writing and reading are set apart from each other so that respective operations of writing and reading are executed virtually in separate memory areas.